low voltage cmos 256k electrically erasable programmable rom 32k x 8 bit eeprom addresses (a0 - a14) the addresses are used to select an 8 bits memory location during a write or read opera- tion. output enable (oe) the output enable input activates the output buff- ers during the read operations. chip enables (ce) the chip enable input must be low to enable all read/write operation on the device. by setting ce high, the device is disabled and the power con- sumption is extremely low with the standby cur- rent below 35 a. features: ? 200 ns access time ? automatic page write operation internal control timer internal data and address latches for 64 bytes ? fast write cycle times byte or page write cycles: 10 ms time to rewrite complete memory: 5 sec typical byte write cycle time: 160 sec ? software data protection ? low power dissipation 20 ma active current 35 a cmos standby current ? direct microprocessor end of write detection data polling ? high reliability cmos technology with self redundant eeprom cell typical endurance: 100,000 cycles data retention: 10 years ? ttl and cmos compatible inputs and outputs ? single 3.3 v 10% power supply for read and programming operations ? jedec approved byte-write pinout description: the turbo ic 28lv256 is a 32k x 8 eeprom fabricated with turbos proprietary, high reliability, high performance cmos technology. the 256k bits of memory are organized as 32k by 8 bits. the device offers access time of 200 ns with power dissipation below 66 mw. the 28lv256 has a 64-bytes page write operation, enabling the entire memory to be typically written in less than 5.0 seconds. during a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other microprocessor operations. the programming process is automatically controlled by the device using an internal control timer. data polling on one or all i/o can be used to detect the end of a programming cycle. in addition, the 28lv256 includes an user-optional software data write mode offering additional protection against unwanted (false) write. the device utilizes an error protected self redundant cell for extended data retention and endurance. write enable (we) the write enable input initiates the writing of data into the memory. data input/output (i/o0-i/o7) data input/output pins are used to read data out of the memory or to write data into the memory. pin description turbo ic, inc. 28lv256 4 3 5 2 1 6 7 8 9 10 11 12 13 30 31 32 a8 a9 a11 nc oe a10 ce i/o7 i/o6 a6 a5 a4 a3 a2 a1 a0 nc i/o0 i/o1 i/o2 gnd nc i/o3 i/o4 i/o5 a12 a7 a14 nc vcc we a13 32 pins plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a10 i/o7 i/o5 i/o3 i/o2 i/o0 a1 a2 a0 i/o1 gnd i/o4 i/o6 ce oe a9 a13 vcc a12 a6 a4 a3 a5 a7 a14 we a8 a11 28 pins pdip 28 pins soic (sog) 28 pins tsop 14 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
device operation read: the 28lv256 is accessed like a static ram. read operations are initi- ated by both ce and oe going low and terminated by either ce or oe returning high. the outputs are at the high impedance state whenever ce or oe returns high. the two line control architecture gives designers flexibility in preventing bus contention. write: a write cycle is initiated when ce and we are low and oe is high. the address is latched internally on the falling edge of ce or we whichever occurs last. the data is latched by the rising edge of ce or we whichever occurs first. once a byte write cycle has been started, the internal timer automatically generates the write sequence to the completion of the write operation. page write operation: the page write operation of 28lv256 allows one to 64 bytes of data to be serially loaded into the device and then simultaneously written into memory during the internally generated write cycle. after the first byte has been loaded, successive bytes of data may be loaded until the full page of 64 bytes is loaded. each new byte to be written must be loaded within 200 s of the previously loaded byte. the page address defined by the ad- dresses a6-a14 is latched by the first ce or we falling edge which ini- tiates a writing cycle and they will stay latched until the completion of the page write. any changes in the page addresses during the load-write cycle will not affect the initially latched page addresses. addresses a0 - a5 are used to define which bytes will be loaded and written within the 64 bytes page. the bytes may be loaded in any order that is convenient to the user. the content of a loaded byte may be altered at any time during the loading cycle if the maximum allowed byte-load time (200 s) is not exceeded. only loaded bytes within the page will be written; no rewriting will occur to the non-selected bytes in the page. data polling: the 28lv256 features data polling to indicate the completion of a write cycle to the host system. during a byte or page write cycle, an attempted read of the last byte loaded into the page will result in the complement of the loaded byte on all outputs i/o0 - i/o7 (i.e. loaded data 01010110, read data 10101001). data polling feature may be used by an attempted read on one or more outputs (whatever is convenient for the system developer). once the write cycle has been completed, true data is valid on all outputs and the next cycle may be started. data protection: the 28lv256 has three hardware features to protect the written content of the memory against inadvertent writes : a.) vcc threshold detector: if vcc is below 2.5 v, the write capa- bilities of the chip is inhibited for whatever input conditions. b.) noise protection: a we, oe, or ce pulse less than 10 ns in width is not able to initiate a write cycle. c.) write inhibit: holding oe at low, or ce at high, or we at high inhibits the write cycle. software write protection: the 28lv256 offers a software controlled data write protection feature. the device is delivered to the user with the software data write protection disabled; i.e. the device will go to the data write operation as long as vcc exceeds 2.5 v and ce, we, and oe inputs are set at write mode levels. the 28lv256 can be automatically protected against an accidental write operation during power-up or power-down without any external cir- cuitry by enabling the software data write protection features. this features is enabled after the first write cycle which includes the software algorithm. after this operation is done, the data write function of the device may be performed only if every page write cycle is preceded by the software algo- rithm. the device will maintain its software protect feature for the rest of its life unless that the software algorithm for disabling the protection is imple- mented. software algorithm: the 28lv256 has an internal register for the software algorithm which en- ables the memory to provide the user with additional features: a.) software write protect enable a sequence of three dummy data writes to the memory will activate internal eeprom fuses during the first page write cycle. these ee- prom fuses will reject any write attempts of new pages of data unless the three dummy data writes are repeated at the beginning of any page writes. the timing for the dummy data and addresses must be the same as for a normal write operation. a violation of the three steps write protect sequence in data or address timing and content will abort the procedure and reset the device to the starting point condition. note: after the three dummy data writes, at least one page load/ write cycle must be performed. if no additional page data is added to the three dummy data writes, the software write protect will not be enabled until the next write, which will not be protected. table 1 shows the required procedure for enabling the software write protect: step mode address a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex a0 hex 4-67 page write address data b.) software write protect disable the software algorithm of 28lv256 includes a six steps sequence of dummy data writing to disable the software write protect feature de- scribed in a.). the six steps write sequence shown in table 2 must be performed at the beginning of a page write cycle. a violation of the six steps write sequence in data or address timing and content will abort the procedure and reset the chip to the starting point con- dition. after a page write cycle including the six steps write sequence has been performed, the 28lv256 does not require the use of three dummy data writes described in a.) for the following page write cycle. the device is at the software write protect disabled state. note: after the six dummy data writes, at least one page load/ write cycle must be performed. if no additional page data is added to the six dummy data writes, the software write protect disable will not be activated. table 2 shows the required procedure for dis- abling the software write protect: step mode address a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 20 hex 7-70 page write address data c.) software chip clear the software algorithm of 28lv256 includes a sequence of six steps dummy data writing to perform a chip clear operation. table 3 shows the six steps write sequence to perform the software chip clear op- eration: step mode address a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 10 hex at the end of the six steps write sequence shown in table 3, the device automatically activates its internal timer to control the chip turbo ic, inc. 28lv256
erase cycle; typically takes 20 msec. after a software chip clear op- eration has been completed, all 256k bit locations of memory show high level at read operation mode. d.) software autoclear disable mode this software algorithm disables the internal automatic clear before write cycle. table 4 shows the six steps needed to perform the auto- clear disable mode: step mode address a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 40 hex 7-70 page write address data page write operation using the software autoclear disable mode will reduce programming time to typically 5 msec. the page write using software autoclear disable mode is usually used after a chip clear or a software chip clear operation. at the end of the six steps sequence, the autoclear before write is disabled and will stay that way unless a power-down occurs or the software autoclear enable procedure is initiated. e.) software autoclear enable mode automatic page clear before page write can be restored to 28lv256 either by vcc power-down or by software autoclear enable mode. table 5 shows the six steps page write procedure needed to enable software autoclear mode: step mode address a14-a0 data i/o 7-0 1 page write 5555 hex aa hex 2 page write 2aaa hex 55 hex 3 page write 5555 hex 80 hex 4 page write 5555 hex aa hex 5 page write 2aaa hex 55 hex 6 page write 5555 hex 50 hex 7-70 page write address data symbol parameter condition min max units icc active vcc ce=oe=vil; all i/o 20 (c) ma current open, min read or 30 (i) ma write cycle time 50 (m) ma isb1 cmos ce=vcc-0.3 v to 35 (c) a standby vcc+1 v 50 (i&m) a current iil input 1 a leakage current iol output 10 a leakage current vil input low -0.1 -0.6 v voltage vih input high 1.8 vcc+0.3 v voltage vol output low iol=1.6 ma 0.3 v voltage voh output high ioh=-0.1 ma 1.8 v voltage d.c. characteristics (c) = commercial (i) = industrial (m) = military turbo ic, inc. 28lv256 absolute maximum stress ranges * temperature storage: -65 c to 150 c under bias: -55 c to 125 c all input or output voltages with respect to vss +6 v to -0.3 v absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operation section of this specifica- tion is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature range : commercial: 0 c to 70 c industrial: -40 c to 85 c military: -55 c to 125 c vcc supply voltage : 3.3 v 10% endurance: 100,000 cycles/byte (typical) data retention : 10 years a.c. characteristics - read operation 28lv256-3 28lv256-4 28lv256-5 28lv256-6 symbol parameters min max min max min max min maxunit tacc address to 200 250 300 400 ns output delay tce ce to output 200 250 300 400 ns delay toe oe to output 110 150 150 150 ns tdf oe to output 0 90 0 90 0 90 0 90 ns in high z toh output hold 0000ns from address changes, chip enable or output enable whichever occurs first a.c. read wave forms a.c. test conditions output load : 1 ttl load and cl=100 pf input rise and fall times : < 10 ns input pulse level : 0 v to 3 v timing measurement reference level : 1.5 v tacc address valid address ce oe output high-z toe tce tdf toh output valid high-z
turbo ic products and documents 1. all documents are subject to change without notice. please contact turbo ic for the latest revision of documents. 2. turbo ic does not assume any responsibility for any damage to the user that may result from accidents or operation under abnormal conditions. 3. turbo ic does not assume any responsibility for the use of any circuitry other than what embodied in a turbo ic product. no other circuits, patents, licenses are implied. 4. turbo ic products are not authorized for use in life support systems or other critical systems where component failure may endanger life. system designers should design with error detection and correction, redundancy and back-up features. a.c. write characteristics symbol parameter min max units tas address set-up time 20 ns tah address hold time 100 ns tcs write set-up time 0 ns tch write hold time 0 ns tcw ce pulse width 150 ns twp we pulse width 150 ns toes oe set-up time 20 ns toeh oe hold time 20 ns tds data set-up time 50 ns tdh data hold time 10 ns tblc byte load cycle 0.2 200 s tlp last byte loaded to data polling output 500 s twc write cycle time 10 ms twc write cycle time (ind & mil) 15 ms part numbers & order information 28lv256pc-4 speed -3 200 ns -4 250 ns -5 300 ns -6 400 ns temperature c -commercial i -industrial m -military package j -plcc p -pdip s -soic t -tsop turbo ic, inc. 2365 paragon drive, suite i, san jose, ca 95131 phone: 408-392-0208 fax: 408-392-0207 see us at www.turbo-ic.com 32k x 8 eeprom page mode write wave form page mode write characteristics symbol parameter min max unit twc write cycle time 10 ms tas address set-up time 20 ns tah address hold time 100 ns tds data set-up time 50 ns tdh data hold time 0 ns twp write pulse width 150 ns tblc byte load cycle time 0.2 200 s chip clear wave form the content of the 28lv256 may be altered to high by the use of the chip clear operation. by setting ce to low, oe to 12 volts, and we to low, the entire memory can be cleared (written high) within 20 ms. the chip clear operation is a latch operation mode. after the chip clear starts, the internal chip timer takes over and completes the clear with- out ce, oe and we being held active. a.c. write characteristics ce-controlled a.c. write characteristics we-controlled oe address ce we data toes tas tcs tah toeh tch twp tds tblc twc tdh high-z data valid high-z valid oe address ce we data toes tas tcs tah toeh tch twp tds tblc twc tdh high-z data valid high-z valid oe ce we a0-a5 data twp tblc tah tas tds tdh byte-0 byte-1 byte-2 ad-valid ad-valid ad-valid oe ce we ts= 20 ns tp= 200 ns th= 20 ns vh=12.0 v0.5v tp th vh vih vih vil vih vil ts turbo ic, inc. 28lv256 rev. 3.0 - 10/28/01
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